1. Field of the Invention
The present invention relates to a solid state imaging device. In particular, it relates to a solid state imaging device which makes it possible to increase the number of pixels and the packaging density without increasing the chip size.
2. Description of Related Art
Hereinafter, an explanation of a conventional solid state imaging device will be provided with reference to the drawing (see Japanese Unexamined Patent Publication No. 2004-207804). FIG. 10 shows a plane structure of a solid state imaging device using a common charge-coupled device (CCD).
The solid state imaging device includes a plurality of pixels (sensor) 111 formed in a matrix on a semiconductor chip 101 and vertical transfer registers 112 extending in the column direction between the sensors 111 adjacent to each other. A horizontal transfer register 113 is arranged in the direction orthogonal to the vertical transfer registers 112 at the end of the vertical transfer registers 112.
At the periphery of a device region 102 of the semiconductor chip 101 in which the pixels 111, vertical transfer registers 112 and horizontal transfer register 113 have been formed, an output buffer 114 is provided and connected to the end of the horizontal transfer register 113 to transfer signal charge received from the horizontal transfer register 113 into a voltage signal for output.
Further, interconnects for supplying a drive signal to the vertical transfer registers 112 and the horizontal transfer register 113 are provided in an interconnect region 103 and a plurality of pads 115 for external connection are provided in a pad region 104 outside the interconnect region 103.
In FIG. 10, only a few pixels 111, vertical transfer registers 112 and pads 115 are shown for simplification. The number of the horizontal transfer register 113 is not limited to one. In some cases, a plurality of horizontal transfer registers 113 may be formed.
Next, with reference to the drawing, an explanation of the structure of a common bonding pad aimed at the reduction of chip size (see Japanese Unexamined Patent Publication No. S57-87145).
FIG. 11 is a sectional view illustrating the structure of a conventional semiconductor device. As shown in FIG. 11, a drain region 121 and a source region 122 made of an impurity diffusion layer are formed in the surface of a semiconductor chip 120 to be spaced from each other and a gate electrode 123 is formed between the drain region 121 and the source region 122 to provide a transistor. Electrode wires 124 and 125 are connected to the drain region 121 and the source region 122, respectively. The gate electrode 123 and the electrode wires 124 and 125 are covered with an interlayer insulating film 126 and a pad 127 for external connection is formed on the interlayer insulating film 126 to overlap the transistor.
As the device region and the pad region vertically overlap, the ratio of the device region to the chip area increases, thereby increasing the packing density of the chip.
In electronic industry, there is a great demand for devices with reduced size and higher performance. In the field of semiconductors, what is required is an increase in packing density of the chip, i.e., reduction in chip size with the performance unchanged and improvement in performance with the chip size unchanged.
From this aspect, in a semiconductor device including a solid state imaging device, components of the device such as impurity diffusion regions, transfer electrodes and interconnects have been miniaturized in order to reduce the chip size and improve the performance with the chip size unchanged.
However, the miniaturization of the impurity diffusion regions and the interconnects leads to deterioration in characteristic of the transistor. In addition, new facilities and new processes must be introduced and the cost increases. If the impurity diffusion regions serving as the pixels of the solid state imaging device are reduced in size, the amount of incident light decreases. As a result, the solid state imaging device deteriorates in sensitivity, saturation characteristic and S/N characteristic, which are important characteristics of the solid state imaging device.
The size of a semiconductor chip depends on the size of the device region in which active elements and passive elements are formed and the size of the pad region provided at the periphery of the device region in which bonding pads for wire bonding are formed. Therefore, in order to achieve both of the reduction of the chip size and the increase of the number of the pixels, it is effective to increase the ratio of the device region to the chip area, i.e., to make the pad region small.
However, if the pad structure as disclosed by Japanese Unexamined Patent Publication No. S57-87145 is applied to the conventional solid state imaging device of Japanese Unexamined Patent Publication No. 2004-207804, light incident on the pixels is cut off by the pads. As a result, the sensitivity and the saturation characteristic which are important for the solid state imaging device deteriorate.